Integrated circuits are made up of literally millions of active devices such as transistors and capacitors. These devices are initially isolated from each other, and are later interconnected to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnect structures are increasingly determining the limits of performance and the density of modern integrated circuits.
On top of the interconnect structures, bond pads or metal bumps are formed and exposed on the surface of the respective chip. Electrical connections are made through the bond pads/metal bumps to connect the chip to a package substrate or another die. The electrical connections may be made through wire bonding or flip-chip bonding.
Wafer level chip scale packaging (WLCSP) is currently widely used for its low cost and relatively simple processes. In a typical WLCSP, interconnect structures are formed on metal layers, followed by the formation of under-bump metallurgy (UBM), and the placement and the reflow of solder balls.
The cost for forming the UBM is typically high. The formation of the UBM, however, could not be skipped since the removal of the UBM results in several problems, and the resulting package may fail in the reliability tests.